Senior ASIC Verification Engineer @ Irvine, CA or Los Altos, CA

Overview
Reporting to: Verification Manager, VLSI Engineering
Location: Irvine, CA or Los Altos, CA

No of Position : 8 Nos
Company
Our client is a profitable pre-IPO semiconductor company headquartered in Southern California with a satellite office in the Bay Area. They are a leading innovator within high performance optical network SoC development with a truly industry differentiating technology and first-to-market commercial chipsets in production as well as an exciting R&D pipeline which is positioning them for strong growth. The company is backed by tier one VCs and sells to world leading telecommunications equipment providers. The company provides an exciting work environment with a world class engineering and management team.
Job Description
Responsible for the development of leading edge verification methodologies for complex high speed networking SoCs. Your duties will include, but are not limited to:
Design and implement verification test bench infrastructure and test cases for system, chip and block level verification, using the latest tools and SystemVerilog class libraries such as OVM, UVM, and VMM.
Implement Pseudo-random and functional coverage verification methodologies
Develop functional test and verification plans.
Work closely with the VLSI Design team to plan and implement design verification strategies.
Qualfications
Must be proficient in Pseudo-random and functional coverage verification methodologies
Strong working knowledge of SystemVerilog and its class class libraries such as UVM (Universal Verification Methodology), OVM (Open Verification Methodology) or VMM (Verification Methodology Manual )
At least 5 years experience as a verification engineer is a must.
At least 2 years hands-on experience of AVM, OVM, UVM, VMM or Specman is a must.
Good communication skills
Other Desirable Traits
Framer experience with SONET or OTN
Networking domain knowledge (e.g. Ethernet, ATM, SONET, GFP, OTN)
SVA, PSL or OVL assertions
SystemC or C++ experience
Formal model checking tools (e.g. Cadence IFV, Jasper)
DSP is a plus
Knowledge of SystemVerilog assertions is desirable.
Domain knowledge is desirable : telecom or networking background such as Ethernet, ATM, Sonet etc. OTN would be ideal but unexpected.

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SR. DEVELOPMENT DATABASE ENGINEER @San Diego, CA

SR. DEVELOPMENT DATABASE ENGINEER
Location San Diego, CA

No of Position : 6 Nos
Job Description
A Senior Development Database Engineer will participate in the creation of a large product suite that enables content protection and security for video delivered via satellite, cable, or the Internet. In particular, the engineer is responsible for designing and developing data models, stored procedures, and scripts to support new applications and enhance existing applications; solving problems both for internal and external clients, and maintaining and enhancing our use of Oracle RAC and Dataguard. The engineer will review requirements, develop the architecture and design of features (including the relevant documentation), develop prototypes, participate in design and code reviews, and program (including unit testing). The engineer must be able to demonstrate technical excellence in his/her personal work as well as contribute to the team’s continued success by sharing technical knowledge. The engineer must be able to follow our development process and contribute to its implementation. The engineer must be able to provide constructive criticism and feedback to colleagues in design and code reviews (in group settings as well as one-on-one) as well as be able to receive constructive criticism and feedback from colleagues. The engineer must be willing to work on existing applications (including defect repairs) as well as develop new features. The engineer must be able to travel occasionally. The engineer must be able to take direction and be able to work independently to implement. The engineer must be able to communicate professionally and positively with clients.
Duties and Responsibilities Develop and maintain Java and C++ DAO libraries Develop recognized, industry-standard best practice solutions for data archival Optimize and manage the performance of the database, through data engineering and performance analysis Develop the database portions of new enhancements to products in the suite of applications including participating in requirement review, design, and development Provide maintenance on existing database structure and code for products in the suite of applications Provide a third-tier of support for the database portion of the products in the suite of applications Play a supporting role in product architecture design, assisting the architecture team with feedback as necessary Operates as a mentor to associate database and software engineers, providing an open learning environment for cross-team knowledge sharing Share technical knowledge in both one-on-one and group settings Play a vocal role in design and code reviews for products throughout the suite of applications Participate in creating and maintaining department standards for software development best practices
http://www.futuristicit.com
Estimate and plan development tasks, improve development processes and tools to meet corporate targets Provide accurate, timely, and detailed work notes and status in the company issue tracking system Create and review documentation for both internal and customer-facing documentation for best practices, configuration and deployment Develop tools for engineering and Global services to help monitor, upgrade and ensure a healthy product deployment Others as assigned
Qualifications 8 + years software engineering work experience 5 + years experience as a DBA for an RDBMS 5 + years SQL querying and scripting experience 4 + years PL-SQL stored procedure development 3 + years data modeling experience 3 + years query optimization 2 + years programming C/C++, Java, or Objective C 2 + years Oracle RAC and Dataguard experience 2 + years of experience architecting and maintaining highly available database clusters Self-directed, capable of independent work Excellent communication skills including documentation Bachelors degree in computer science or related field or equivalent experience
Preferred Digital Rights Management Experience in a security organization JDBC NoSQL OCI ODBC Oracle certification Server and application programming in Linux, OS X, or Windows Service-oriented architecture Video Conditional Access Systems Video standards such as: DECE/UltraViolet, MPEG2/4, AVC, H.264, MPEG DASH, HTTP Live Streaming, PlayReady, Marlin and RTSP Virtualization Windows Media.

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Principal ASIC Design Engineer ,@ Irvine, CA or Los Altos, CA

Principal ASIC Design Engineer
Overview
Reporting to: Director, VLSI Engineering
Location: Irvine, CA or Los Altos, CA
Job Description
The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can in cludevector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs. Typical activities include coding and verification of DSP block models (‘C’, ‘C++’, Matlab), RTL coding, writing verification plans and execution, synthesis, formal verification (LEC) and static timing analysis. Successful candidate will have strong working knowledge in ASIC design, implementation and verification, DSP algorithms preferably used in optical networking, OTN standards, and DSP algorithm modeling.
Qualifications The successful candidate will be experienced with the IC/ASIC design/verification flow through at least three project cycles from concept through production release of silicon Extensive hands-on experience with synthesis, formal verification, static timing analysis, DFT (scan, JTAG, memory BIST) logic insertion. This includes synthesis, LEC, STA flow setup Strong working knowledge in DSP algorithms preferably used in optical PHYs (timing recovery, feed forward equalizers, carrier recovery, FEC etc.), modeling and model verification Fluency with Verilog, System Verilog or VHDL. Knowledge in SystemC, ‘C’, ‘C++’ or Matlab highly desirable Experience in RTL debugging using conventional EDA tools like Cadence IES, Mentor Graphics Modelsim or Synopsys VCS Strong working knowledge in various hardware development tools like Synopsys Design Compiler, Primetime and Formality, or Cadence RTL Compiler and Conformal compulsory The engineer must have a well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements Good knowledge of scripting in tcl or Perl Experience with low power design and verification flows highly desirable Bachelor’s in Engineering or equivalent required.

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Principal Physical Design Engineer @Irvine, CA or Los Altos, CA

No: of Position : 10 Nos
Overview
Reporting to: Director, Physical Design
Location: Irvine, CA or Los Altos, CA
Job Description
The engineer will be responsible for implementing tool flows and developing CAD methodologies generating flows & scripts. He/she will handle evaluation of tools in the development of new tool flows, and will also be responsible for managing related day to day timing closure/backend activities in meeting project schedules. The engineer will be required to code in scripting languages, TCL and Unix shell languages. Other script languages such as awk, perl, and C are a plus. In addition, the engineer will perform the following ASIC design tasks: Full chip level floorplanning/prototyping, integration and layout Block level layout and timing closure Static Timing/Crosstalk Analysis and timing closure Synthesis/Physical Synthesis Power/IR/EM analysis Physical verification (LVS/DRC/ERC) ECO implementation
Qualifications Must understand chip layout/physical design concepts, methodologies and flows (i.e. floorplanning, power planning, power/IR/EM analysis, custom routing, pad ring etc.) Must have an understanding of static timing and crosstalk/noise analysis and timing closure concepts, methodologies and flows. Must have an understanding of RTL/gate synthesis concepts, methodologies and flows. Solid hands on experience with the following areas of design: Layout, place and route Static timing/crosstalk analysis RTL/gate synthesis Physical verification Power/IR/EM analysis Hands on experience with following layout CAD tools is a must: Layout: Aprisa, Talus, ICC OR FirstEncounter Synthesis: Design Compiler OR RTL Compiler Static timing: Primetime, Tekton, Goldtime Minimum 10 years of experience with BSEE or 7 years’ experience with MSEE

 

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MEP Engineer for an upcoming 5 star hotel in Chennai

  1. Coordinate and monitor the MEP activities with the project schedule for proper flow of work on site.
  2. Coordinate with the Key Account Manager, Project Manager, client, contractors, suppliers and other relevant parties.
  3. Report internally to Project Manager and assist in meeting at clients engineering and stakeholder level.
  4. Manage the Pre-Construction review meetings with contractor and supplier. Provide required advice on MEP design issues to client / design consultant arising during construction.
  5. Participate in Weekly Progress Meeting with Project Manager and the contractors.
  6. Support the Project Manager to review site safety plans and JSAs, carry out safety inspections during construction, document findings and implement recommendations for improvement. Where safety standards are not compliant, take strong measures to achieve compliance.
  7. Review construction schedules, monitor and report on the progress of work to the project manager.
  8. Participate in site meetings, reviews inspection schedule, complete inspection and checklists and witness commissioning testing of systems / equipment.
  9. Execution of MEP services according to the detailed drawings and site conditions.
  10. Preparation of materials delivery status reports and daily/weekly progress reports.
  11. Planning and execution of shutdown activities for technical assets and services.
  12. Preparation of close out reports and lessons learned assessment.