Principal Physical Design Engineer @Irvine, CA or Los Altos, CA

No: of Position : 10 Nos
Reporting to: Director, Physical Design
Location: Irvine, CA or Los Altos, CA
Job Description
The engineer will be responsible for implementing tool flows and developing CAD methodologies generating flows & scripts. He/she will handle evaluation of tools in the development of new tool flows, and will also be responsible for managing related day to day timing closure/backend activities in meeting project schedules. The engineer will be required to code in scripting languages, TCL and Unix shell languages. Other script languages such as awk, perl, and C are a plus. In addition, the engineer will perform the following ASIC design tasks: Full chip level floorplanning/prototyping, integration and layout Block level layout and timing closure Static Timing/Crosstalk Analysis and timing closure Synthesis/Physical Synthesis Power/IR/EM analysis Physical verification (LVS/DRC/ERC) ECO implementation
Qualifications Must understand chip layout/physical design concepts, methodologies and flows (i.e. floorplanning, power planning, power/IR/EM analysis, custom routing, pad ring etc.) Must have an understanding of static timing and crosstalk/noise analysis and timing closure concepts, methodologies and flows. Must have an understanding of RTL/gate synthesis concepts, methodologies and flows. Solid hands on experience with the following areas of design: Layout, place and route Static timing/crosstalk analysis RTL/gate synthesis Physical verification Power/IR/EM analysis Hands on experience with following layout CAD tools is a must: Layout: Aprisa, Talus, ICC OR FirstEncounter Synthesis: Design Compiler OR RTL Compiler Static timing: Primetime, Tekton, Goldtime Minimum 10 years of experience with BSEE or 7 years’ experience with MSEE


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