Principal ASIC Design Engineer
Reporting to: Director, VLSI Engineering
Location: Irvine, CA or Los Altos, CA
The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can in cludevector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs. Typical activities include coding and verification of DSP block models (‘C’, ‘C++’, Matlab), RTL coding, writing verification plans and execution, synthesis, formal verification (LEC) and static timing analysis. Successful candidate will have strong working knowledge in ASIC design, implementation and verification, DSP algorithms preferably used in optical networking, OTN standards, and DSP algorithm modeling.
Qualifications The successful candidate will be experienced with the IC/ASIC design/verification flow through at least three project cycles from concept through production release of silicon Extensive hands-on experience with synthesis, formal verification, static timing analysis, DFT (scan, JTAG, memory BIST) logic insertion. This includes synthesis, LEC, STA flow setup Strong working knowledge in DSP algorithms preferably used in optical PHYs (timing recovery, feed forward equalizers, carrier recovery, FEC etc.), modeling and model verification Fluency with Verilog, System Verilog or VHDL. Knowledge in SystemC, ‘C’, ‘C++’ or Matlab highly desirable Experience in RTL debugging using conventional EDA tools like Cadence IES, Mentor Graphics Modelsim or Synopsys VCS Strong working knowledge in various hardware development tools like Synopsys Design Compiler, Primetime and Formality, or Cadence RTL Compiler and Conformal compulsory The engineer must have a well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements Good knowledge of scripting in tcl or Perl Experience with low power design and verification flows highly desirable Bachelor’s in Engineering or equivalent required.
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