Senior ASIC Verification Engineer @ Irvine, CA or Los Altos, CA

Overview
Reporting to: Verification Manager, VLSI Engineering
Location: Irvine, CA or Los Altos, CA

No of Position : 8 Nos
Company
Our client is a profitable pre-IPO semiconductor company headquartered in Southern California with a satellite office in the Bay Area. They are a leading innovator within high performance optical network SoC development with a truly industry differentiating technology and first-to-market commercial chipsets in production as well as an exciting R&D pipeline which is positioning them for strong growth. The company is backed by tier one VCs and sells to world leading telecommunications equipment providers. The company provides an exciting work environment with a world class engineering and management team.
Job Description
Responsible for the development of leading edge verification methodologies for complex high speed networking SoCs. Your duties will include, but are not limited to:
Design and implement verification test bench infrastructure and test cases for system, chip and block level verification, using the latest tools and SystemVerilog class libraries such as OVM, UVM, and VMM.
Implement Pseudo-random and functional coverage verification methodologies
Develop functional test and verification plans.
Work closely with the VLSI Design team to plan and implement design verification strategies.
Qualfications
Must be proficient in Pseudo-random and functional coverage verification methodologies
Strong working knowledge of SystemVerilog and its class class libraries such as UVM (Universal Verification Methodology), OVM (Open Verification Methodology) or VMM (Verification Methodology Manual )
At least 5 years experience as a verification engineer is a must.
At least 2 years hands-on experience of AVM, OVM, UVM, VMM or Specman is a must.
Good communication skills
Other Desirable Traits
Framer experience with SONET or OTN
Networking domain knowledge (e.g. Ethernet, ATM, SONET, GFP, OTN)
SVA, PSL or OVL assertions
SystemC or C++ experience
Formal model checking tools (e.g. Cadence IFV, Jasper)
DSP is a plus
Knowledge of SystemVerilog assertions is desirable.
Domain knowledge is desirable : telecom or networking background such as Ethernet, ATM, Sonet etc. OTN would be ideal but unexpected.

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